View MR44V064B_9058843.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fedr44v064b-01 issue date: jan. 08, 2016 MR44V064B 64k(8,192-word 8-bit) feram (ferroelectric random access memory) i2c 1/16 general description the MR44V064B is a nonvolatile 8,19 2-word x 8-bit ferroelectric ran dom access memory (feram) developed in the ferroelectric process and s ilicon-gate cmos technology. the mr 44v064b is accessed using two-wire serial interface ( i2c bus ).unlike srams, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. this device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various eeproms. therefore, the wr ite cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. the MR44V064B can be used in various applications, because the device is guar anteed for the write/read tolerance of 10 12 cycles per bit and the rewrite co unt can be extended significantly. features ? 8,192-word 8-bit configuration i2c bus interface ? a single 3.3 v typ (1.8v to 3.6v) power supply ? operating frequency: 3.4mhz(max) hs-mode 1mhz(max) f/s-mode plus ? read/write tolerance 10 12 cycles/bit ? data retention 10 years ? guaranteed operating temperature range ? 40 to 85 c (extended temperature version) ? package options: 8-pin plastic sop (p-sop8-200-1.27-t2k)
fedr44v064b-01 MR44V064B 2/16 pin configuration pin descriptions pin name description a0 ? a2 address ( input ) address pin indicates device address. when address value is match the device address code from sda, the device will be selected. the address pins are pulled down internally. sda serial data input serial data output ( input / output ) sda is a bi-directional line for i2c interface. the output driver is open-drain. a pull-up resistor is required. scl serial clock ( input ) serial clock is the clock input pin for setting for serial data timing. inputs are latched on the rising edge and outputs occur on the falling edge. wp write protect ( input ) write protect pin controls writ e-operation to the memory. when wp is high, all address in the memory will be protected. when wp is low, all address in the memory will be written. wp pin is pulled down internally. v cc , v ss power supply apply the specified voltage to v cc . connect v ss to ground. 8-pin plastic sop a0 a1 a2 vss vcc wp scl sda 1 8 2 7 3 6 4 5 MR44V064B
fedr44v064b-01 MR44V064B 3/16 i2c bus the MR44V064B employs a bi-directional two-wire i2c bus interface, works as a slave device. an example of i2c interf ace system with MR44V064B i2c bus comunication i2c bus data communication starts by start condition input , and ends by stop condition input. data is always 8bit long, acknowledge is always required after each by te. i2c bus carries out data transmission with plural devices connected by 2 communication lines of serial data ( sda ) and serial clock ( scl ). start condition before executing each command, start condition ( start bit ) where sda go es from ?high? down to ?low? when scl is ?high? is necessary. MR44V064B always detects whether sda and scl are in start condition ( start bit ) or not, therefore, unless this condition is satisfied, any command is executed. stop condition each command can be ended by sda rising from ?low? to ?high? when stop condition ( stop bit ), namely,scl is ?high?. scl sda start condition 1-7 8 9 1-7 8 9 1-7 8 9 stop condition address r/w ack data ack data ack scl sda pull-up resistor scl sda i2c bus master scl sda MR44V064B (slave) a2 a1 a0 0 0 0 scl sda MR44V064B (slave) a2 a1 a0 0 0 1
fedr44v064b-01 MR44V064B 4/16 acknowledge ( ack ) signal this acknowledge ( ack ) signal is a software rule to show whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write command, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. the device (this ic at slave address input of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda ?l ow? during 9 clock cycles , and outputs acknowledge signal ( ack signal) showing that it has received the 8bit data. this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( ack signal) ?low?. each write action outputs ac knowledge signal ( ack signal ) ?low?, at receiving 8bit data ( word address and write data ). each read action outputs 8bit data ( read data ), and detects acknowledge signal ( ack signal ) ?low?. when acknowledge signal ( ack signal ) is detect, and stop condition is not sent from the master ( -com) side, this ic continues data output. when acknowledge signal ( ack signal ) is not detected, this ic stops data transfer, and recognizes stop condition ( stop bit ), and ends read action. and this ic gets in status. slave address output slave address after st art condition from master. the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to ?1010?. next slave addresses (a2 a1 a0 ? device address) are for selecting devices, and plural ones can be used on a same bus according to the num ber of device addresses. the most insignificant bit (r/w?read/write) of slave ad dress is used for designating write or read action, and is as shown below. setting r/w to 0 write (setting 0 to word address setting of random read) setting r/w to 1 read write protect when wp terminal is set vcc(h level), data rewrite of all addresses is prohibited. when it is set vss(l level), data rewrite of all address is enabled. be sure to connect this terminal to vcc or vss, or control it to h level or l level. at extremely low voltage at power on / off, by setting the wp terminal ?h?, mistake write can be prevented. scl sda start condition 2 3 ack 56 89 7 4 1 12 1 0 0 1 a 2 a 1 a 0r/w
fedr44v064b-01 MR44V064B 5/16 command byte write cycle arbitrary data is written to feram. when to wr ite only 1 byte, byte write is normally used. start condition slave address with lsb is 0 (write) 1 st and 2 nd word address byte of write data. stop condition page write cycle when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. by page write cycle, up to 8,192 bytes data can be written. when data of the maximum bytes or higher is sent, data from the first byte is overwritten. byte write cycle ( hs-mode ) 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k a c k write data 0 0 1 x x 0 0 hs-mode command s t a r t n a c k x 0 0 0 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k a c k write data 0 0 0 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k a c k d 7 d 0 a c k write data write data 0 0 0
fedr44v064b-01 MR44V064B 6/16 random read cycle random read cycle is a command to read data by designating address. start condition slave address with lsb is 0 (write) 1 st and 2 nd word address start condition slave address with lsb is 1 (read) read out byte of data. ack to ?h? stop condition sequential read cycle when ack signal ?l? after d0 is detected, and stop condition is not sent from master side, the next address data can be read in succession. current address read cycle current address read cycle is a comma nd to read data of internal address register without designating address. when the last read or write address is (n)-th address ju st before current read cycl e, the current address read command outputs data of (n+1)-th address. the previous read or write sequence should be complete up to stop condition. current address read cycle ( hs-mode ) the MR44V064B support a 3.4mhz high speed mode. when hs-mode operation is needed, the hs-mode command is required before any command. after the hs-mode command is issued, MR44V064B will be the hs-mode, until stop condition is issued. 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k read data 1 0 a2 a1 a0 10 slave address s t a r t r e a d a c k d 7 a c k d 0 n a c k 0 0 0 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k read data 1 0 a2 a1 a0 10 slave address s t a r t r e a d a c k n a c k 0 0 0 0 0 1 x x 0 0 hs-mode command s t a r t read data d0 d7 s t o p n a c k n a c k 1 0 a2 a1 a0 1 0 slave address s t a r t r e a d a c k x 1 0 a2 a1 a0 1 0 slave address s t a r t r e a d read data d0 d7 s t o p n a c k a c k
fedr44v064b-01 MR44V064B 7/16 electrical characteristics absolute maximum ratings the application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. therefore, do not allow actual characteristics to exceed any one parameter ratings pin voltages parameter symbol rating unit note min. max. pin voltage (input signal) v in ?0.5 v cc + 0.5 v pin voltage (input/output voltage) v inq , v outq ?0.5 v cc + 0.5 v power supply voltage v cc ?0.5 4.0 v temperature range parameter symbol rating unit note min. max. storage temperature (extended temperature version) tstg ?55 125 c operating temperature (extended temperature version) topr ?40 85 c others parameter symbol rating note power dissipation p d 1,000mw ta=25c
fedr44v064b-01 MR44V064B 8/16 recommended operating conditions power supply voltage parameter symbol min. typ. max. unit note power supply voltage v cc 1.8 3.3 3.6 v ground voltage v ss 0 0 0 v dc input voltage parameter symbol min. max. unit note input high voltage v ih v cc x 0.7 v cc 0.3 v input low voltage v il ?0.3 v cc x 0.3 v
fedr44v064b-01 MR44V064B 9/16 dc characteristics dc input/output characteristics parameter symbol condition min. max. unit note output low voltage v ol i ol =3ma D 0.4 v input leakage current i li D ?10 10 a output leakage current i lo D ?10 10 a power supply current v cc =max.to min, ta=topr parameter symbol condition max. unit note power supply current (standby) i ccs scl,sda= v cc , a2,a1,a0= v cc or v ss 10 a power supply current (operating) i cca v in =0.3v or v cc 0.3v, fscl=3.4mhz fscl=1mhz 1 300 ma ua
fedr44v064b-01 MR44V064B 10/16 ac characteristics v cc =max. to min., ta=topr. parameter symbol f/s-mode f/s-mode plus hs-mode unit note min. max. min. max. min. max. clock frequency f scl d.c. 400 d.c. 1000 dc 3400 khz clock low time tlow 1300 500 160 ns clock high time thigh 600 300 60 ns output data delay time taa 900 450 130 ns bus release time before transfer start tbuf 1300 500 300 ns start condition hold time thd:sta 600 250 160 ns start condition setup time tsu:sta 600 250 160 ns input data hold time thd:dat 0 0 0 ns input data setup time tsu:dat 100 100 10 ns sda, scl rise time tr 300 300 80 ns 1 sda, scl fall time tf 300 100 80 ns 1 stop condition setup time tsu:sto 600 250 160 ns output data hold time tdh 0 0 0 ns noise removal time (sda, scl) tsp 50 50 5 ns note: 1. not 100% tested equivalent ac load circuit 3.3v 1.1k ? out p ut 100pf
fedr44v064b-01 MR44V064B 11/16 timing scl sda (input) tr sda (output) tf tsu:dat tlow thigh tbuf taa tdh thd:dat 1/fscl tsp tsp tr tf scl sda (input) tsu:sta thd:sta tsu:sto start bit stop bit
fedr44v064b-01 MR44V064B 12/16 ? power-on and power-off characteristics (under recommended operating conditions) parameter symbol min. max. unit note power-on scl,sda high hold time t vhel 100 ? ns 1, 2 power-off scl, sda high hold time t ehvl 0 ? ns 1 power-on interval time t vlvh 0 ? s 2 v cc power-on ramp rate tr 30 s/v v cc power-off ramp rate tf 30 s/v notes: 1. to prevent an erroneous operation, be sure to ma intain scl=sda="h", and se t the feram in an inactive state (standby mode) before and after power-on and power-off. 2. powering on at the intermediate voltage level will cau se an erroneous operation; thus, be sure to power up from 0 v. 3. enter all signals at the same time as power-on or enter all signals after power-on. ? power-on and power-off sequences 0 v v il max. v cc min. v cc v ih min. scl,sd a 0v v il max. v cc min. v cc v ih min. scl,sda t vhel t vlvh t ehvl t f t r
fedr44v064b-01 MR44V064B 13/16 read/write cycles and data retention (under recommended operating conditions) parameter min. max. unit note read/write cycle 10 12 ? cycle data retention 10 ? year capacitance signal symbol min. max. unit note input capacitance c in ? 10 pf 1 input/output capacitance c out ? 10 pf 1 note1: sampling value. measurement conditions are v in = v out = gnd, f = 1mhz, and ta = 25c
fedr44v064b-01 MR44V064B 14/16 package dimensions notes for mounting the surface mount type package the surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact a rohm sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedr44v064b-01 MR44V064B 15/16 revision history document no. date page description previous edition current edition fedr44v064b-01 jan. 08, 2016 ? ? final edition 1
fedr44v064b-01 MR44V064B 16/16 notes 1) the information contained herein is subject to change without notice. 2) although lapis semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. therefore, in order to prevent personal injury or fire arising fro m failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. lapis semiconductor shall have no responsibility for any damages arising out of the use of our products beyond the rating specified by lapis semiconductor. 3) examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. 4) the technical information specified herein is intended only to show the typical functions of the products and examples of application circuits for th e products. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of lapis semiconductor or any third party with respect to the information contained in this document; therefore lapis semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) the products are intended for use in general electr onic equipment (i.e. av/oa devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) the products specified in this document are not designed to be radiation tolerant. 7) for use of our products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a lapis semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, so lar cells, and power transmission systems. 8) do not use our products in applications requir ing extremely high reliability, such as aerospace equipment, nuclear power control sy stems, and submarine repeaters. 9) lapis semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 10) lapis semiconductor has used reasonable care to ensu re the accuracy of the information contained in this document. however, lapis semiconductor does not warrant that such information is error-free and lapis semiconductor shall have no responsibil ity for any damages arising from any inaccuracy or misprint of such information. 11) please use the products in accordance with any applicable environmental laws and regulations, such as the rohs directive. for more details, includin g rohs compatibility, please contact a rohm sales office. lapis semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) when providing our products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the us export administration regulations and the foreign exchange and foreign trade act. 13) this document, in part or in whole, may not be re printed or reproduced without prior consent of lapis semiconductor. copyright 2016 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

▲Up To Search▲

Price & Availability of MR44V064B

	To Download MR44V064B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .